As the trend of device miniaturization continues, the dimension of a strip conductor such as a metal wiring conductor formed on a semiconductor substrate has become smaller than the light-source wavelength of a drawing exposure apparatus. This has added challenges to the processing of wiring strip conductors in accordance with intended design sizes. In particular, due to the miniaturization and the high-density integration of a mask pattern, the pattern arrangement plays a large role in the process of forming strip conductors through photolithography or etching processing. Optical proximity correction processing (hereinafter, described as OPC processing), in which a correction pattern is preliminarily added to a designed pattern, is generally performed so that the actual size of a processed strip conductor approaches the desirable size of the strip conductor in accordance with design goals.
However, the physical implementation of the connectivity intent of designs is driven by algorithms and design methodologies within the confines of design rules. The routing phase of the integrated circuit (IC) implementation flow creates the connectivity between design elements (transistors, standard cells, or modules) through a multi-level wiring structure which is made up of 2D wiring layers connected by via layers. Routing is performed by automated, computer-aided design (CAD) tools or by designers (who utilize structured or semi-structured design methodologies to create or guide the wiring structure). There is a tradeoff between constrained design rules and layout complexity. It is therefore desirable to have systems and methods for improvements in the generation of layout data of a semiconductor integrated circuit.